1. Field of Invention
The present invention relates to communication systems. In particular, the present invention relates to demodulators which utilize initial phase and/or frequency estimates in a phase locked loop (PLL) tracking the phase and frequency of an input modulated signal.
2. Discussion of the Related Art
In burst communication systems, particularly digital communication systems comprising a communication transmitter for digital data transmission and a communication receiver for digital data reception via a channel, it is known to impress intelligent information to be conveyed onto a carrier for transmission by one of many different modulation techniques, including binary phase shift keying (BPSK) modulation or quaternary phase shift keying (QPSK) modulation. Each burst consists of a preamble portion and a data portion. A demodulator in the communication receiver includes a phase tracking loop (PTL) which determines an initial estimate of the phase of the modulated signal using the preamble portion. The phase tracking loop is initialized with the phase estimate and thereafter constantly calculates an estimate of the transmitter's phase so that it continuously tracks the incoming signal during reception and demodulation of the data portion.
Conventionally, demodulators use one of a number of different phase tracking loops to track and coherently demodulate the modulated signal received from a transmitter so that it may be transformed back into the fixed phase space of the transmitter loops, such as squaring loops, Costas tracking loops, and decision-directed feedback loops for performing phase tracking of either a BPSK or QPSK modulated signal. A commonly used method for performing this type of phase tracking is a digital decision directed phase locked loop (DD-PLL). The basic principle of decision directed phase locked loops (DD-PLLs) is well known as described in the classic “Telecommunication Systems Engineering” text by William C. Lindsey and Marvin K. Simon, originally published by Prentice-Hall in 1973, and the “Digital Communications” text by Kamilo Feher, originally published by Prentice-Hall in 1983 and republished by Noble Publishing Corp. in 1997. Generally, the input to a digital decision directed phase locked loop (DD-PLL) typically consists of only the phase angles of a sequence of complex data sample pairs obtained by down converting the incoming BPSK or QPSK modulated signal to a baseband quadrature (orthogonal) pair, IQ digit combination, passing these through matched filters and sampling the results at the symbol rate. This sampled pair may be considered as a complex variable in rectangular form. The complex variable is converted to polar form to produce the equivalent variable pair. The apparent incoming phase is referenced to the currently estimated phase (i.e. the tracked phase) to form the phase difference. The phase difference between the incoming phase and the estimated phase is influenced by the true difference between the phase systems of the transmitter and the receiver, by phase and thermal noise present at the receiver, and also by the symbol's data content which changes the angle by a multiple of π/2 for QPSK or of π for BPSK. The polar form is then transformed back into the rectangular form, for subsequent processing, including soft decision decoding when error control is being utilized.
In conventional phase tracking circuits, the effect of the data content on the phase difference between the incoming phase and the estimated phase is compensated by making a “hard” decision on the data content of each individual BPSK or QPSK symbol on the rectangular coordinates. A standard phase detector generates phase error measurements for each BPSK or QPSK symbol, based on the hard decision of each symbol. In the absence of noise in the baseband quadrature pair, the estimated phase decision, which is based on each individual BPSK or QPSK symbol, is always correct so that the resultant phase error measurement equals the true difference between the phase systems of the transmitter and the receiver. The value of the resultant phase error measurement is then filtered to yield an updated estimate for use at the next symbol epoch, forming a classical servo loop.
When information is modulated onto a carrier by a binary phase shift keying (BPSK) or quaternary phase shift keying (QPSK) modulation technique, and a BPSK or QPSK modulated signal is transmitted from the transmitter, the phase space of the receiver generally differs from that of the transmitter due to frequency differences between the local oscillators at the transmitter and receiver and the effect of varying delays and frequency shifts in the propagation path between the two sites. The performance of the demodulator in the communications receiver is sensitive to frequency errors between the incoming signal and the demodulator's reference frequency. Increasing frequency error reduces the possibility that the demodulator will successfully demodulate and decoder the data portion of the incoming signal. In addition, noise is always present so that the resultant phase error measurement may be grossly distorted, especially when an incorrect decision is made in converting the phase difference between the incoming phase and the estimated phase to the resultant phase error measurement. As long as the bit error rate (BER) is small, many existing symbol-by-symbol decision directed phase locked loops (DD-PLLs) perform well. However, at low signal-to-noise ratios, the BER can be relatively high which means that the initial phase detection and estimate from the preamble portion of the signal can be quite unreliable. The initial phase error can be as much as +/−30 degrees when phase tracking of the data portion begins. A high initial phase error results in high codeword error rates because it is difficult for the phase locked loop to lock and to correct for large phase errors. The effect of large initial phase errors, together with the large amount of noise entering the loop, may cause the demodulator to perform unacceptably when demodulating and decoding the beginning of the data portion than during the remainder of the data portion. Indeed, the presence of large phase errors, either initially or during tracking, typically results in dropped cells. For burst communication systems, such as time division multiplexed access (TDMA), and especially for satellite communication systems with low signal-to-noise ratios, there is a need to reliably demodulate and decode the data portion of each burst and to reduce the number of dropped cells and the cell loss rate (CLR). Eliminating large errors in the initial phase estimates in the demodulator phase tracking loop can reduce the number of dropped cells. However, in some communications systems, a CLR of 10^(−4) or 10^(−3) is unacceptable and the CLR requirement can be as stringent as 10^(−8). This requirement is difficult because it only allows one in a hundred million cells to be dropped due to effects other than thermal noise. Additional powerful processing techniques may be utilized in the demodulator to achieve more stringent CLR requirements, but much of the processing power is wasted on bursts which may be adequately demodulated and decoded by less powerful techniques and the implementation of the processing power is inefficient.
For at least the above reasons, conventional decision directed phase locked loops (DD-PLLs) may fail to adequately track the phase of a phase shift keying (PSK) modulated signal, and to minimize the error rate for recovered data, especially significant errors which result in dropped cells and unacceptably high CLR. This consequence is particularly damaging for digital communication systems such as satellite communication systems that utilize error correcting codes and large constellation signal sets to communicate at very low signal-to-noise ratios. During testing, it was observed that the failure rate of the demodulation process was relatively high due to errors in codewords at the beginning of the phase tracking operation. FIGS. 8A–8H are diagrams graphically illustrating the probability of a decoding error for each codeword for various sets of variables which specify fain settings used in the DD-PLL.